A semiconductor device manufacturing process includes a process for plasma-etching various films formed on a substrate, e.g., a semiconductor wafer or the like, provided in a processing chamber of a plasma etching apparatus.
In the plasma etching apparatus, the interior of the processing chamber accommodating therein a substrate, e.g., a semiconductor wafer or the like, is set to a depressurized atmosphere of a predetermined pressure and a predetermined processing gas is supplied into the processing chamber. The processing gas is converted to a plasma by a RF (radio frequency) electric field or the like. By applying the plasma of the processing gas to the substrate, various films formed on the substrate are plasma-etched.
As for a plasma processing method using the above plasma etching apparatus or the like, there has been known a method for etching silicon without generating an undercut by forming a nitride film on a surface while temporarily stopping etching by intermittently stopping the supply of SF6 gas in a gaseous mixture supplied into a processing chamber for a short period of time, the SF6 gas serving to facilitate etching (see, e.g., Japanese Patent Application Publication No. H4-73287).
Along with the trend toward miniaturization of a circuit pattern of a semiconductor device, a pattern size has been reduced from about 56 nm to about 43 nm and further to about 32 nm. For that reason, a pattern formed by plasma etching tends to be miniaturized and become increased in height or depth. Therefore, a technique for uniformly forming such pattern with high accuracy and high selectivity has been developed. However, due to the trade-off relationship between the selectivity and the pattern shape, it is difficult to form a pattern, e.g., a thin and deep hole, a line-and-space pattern having a small width and a tall height, or the like, with high selectivity.